As is known in the art, there is a trend for consumer and military vehicle reliance on vehicle mounted radar systems (generally referred to as “automotive radar systems”). With respect to consumer vehicles, radar systems have been found to be particularly suitable in applications for blind spot detection, backup assist, and anti-collision warning systems. Military vehicles have also used automotive radar systems for the aforementioned applications in addition to “threat” detection.
Automotive radar system performance is affected not only by its ability to accurately detect the presence of a vehicle in a blind spot area or detect obstacles in front of a vehicle, for example, but is likewise influenced by external factors, such as its ability to integrate with vehicles, which may depend upon its associated cost, form factor, and energy usage to meet the low size, weight, and power requirements demanded by consumers and military customers alike.
Some automotive radar systems utilize a frequency modulated continuous wave (FMCW) radar technique. Some FMCW radars transmit a linear frequency chirp generated from a tuning voltage applied to a voltage variable capacitor that is part of an oscillator circuit (e.g. a VCO). The tuning voltage necessarily compensates for frequency offset, frequency slope and frequency non-linearity. This voltage comes from the digital to analog converter (DAC) which is then low pass filtered to eliminate high frequency noise. The DAC can use a conventional multi-bit DAC or a single bit DAC. The single bit DAC may convert a 32 MHz bit stream to a bit pattern (i.e. a pattern of logic 0's and 1's) that when filtered produces an analog voltage. In some systems, the single bit approach uses a simulated RC time constant as part of the logic to determine whether to generate a 1 or a 0 in the bit pattern. A bit pattern having the appropriate 1/0 history is then computed to generate the tuning voltage when played back through a bit serializer and tuning voltage filter.
One way to implement a one bit DAC is to utilize a pulse width modulator (PWM) circuit or delta sigma modulator (DSM) circuit to generate the bit stream. A comparator in the PWM circuit or DSM circuit decides whether the next bit should be 1 or 0. To generate an appropriate bit stream, it is possible to simulate feedback with a simulated RC time constant. The so-generated bit stream is stored in memory. The radar FMCW chirp generation occurs when playing back the recorded bit stream though the low pass filter.
A processor can generate a bit stream and provide the bit stream through a serial port. The bit stream is formed from a sequence of words (e.g. a sequence of N bit words). In some applications (e.g. automotive radar applications), the recorded bit stream is provided from two-hundred fifty-six (256) thirty-two (32) bit words that get loaded into a bit serializer at a predetermined rate to produce a desired bit stream. For example, the 256 32-bit words may be loaded into a bit serializer at a 1 MHz rate thereby producing a 32 MHz bit stream.
At bit stream speeds necessary for desired operation in many applications including, but not limited to automotive radar applications, a high speed driver circuit coupled between the serial port of the processor and the VCO is required to process such a bit streams and provide an appropriate signal to drive the VCO.
Such high speed driver circuitry, however, requires a substantial amount of power, a relatively large amount of physical layout space, and a specialized low impedance I/O pin on the processor to which it is coupled.